1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a liquid crystal display (LCD) device and to a method for producing a liquid crystal device, wherein a constant current flows in lines by compensating a resistance value for a line length on pad link lines having different lengths.
2. Discussion of the Background Art
Liquid crystal display (LCD) devices, having advantageous characteristics such as high contrast ratio, great gray level, great picture quality and low power consumption are now the subject of increased research and study. The LCD device is especially suitable for an ultra-thin display device such as a wall-mountable TV. Also, the LCD device has attracted a deal of interest as a new display device that can substitute for a CRT in that the LCD device has a thin profile, is light in weight and has low power consumption. As a result, the LCD device may be used as a display device for a notebook computer operated by a battery.
Generally, the LCD device includes a thin film transistor array substrate having a thin film transistor and a pixel electrode in a pixel region defined by crossing gate and data lines, a color filter substrate having a color filter layer, a black matrix layer and a common electrode, and a liquid crystal layer between the two substrates, wherein liquid crystal molecules of the liquid crystal layer are aligned by applying a voltage to electrodes to control light transmittance, thereby displaying a picture image.
The color filter substrate and the thin film transistor array substrate are bonded to each other by a sealant such as epoxy resin. A driving circuit of a PCB (Printed Circuit Board) is connected with the thin film transistor array substrate in a TCP (Tape Carrier Package) method using a driver IC. On the PCB, a plurality of devices (such as ICs of the substrate), are formed to generate various control signals and data signals for driving the LCD device.
Hereinafter, a background art LCD device will be described with reference to the accompanying drawings.
FIG. 1 is a plane view illustrating a thin film transistor array substrate according to the background art. FIG. 2A and FIG. 2B are cross-sectional views illustrating a thin film transistor array substrate according to the background art.
As shown in FIG. 1, the thin film transistor array substrate 11 includes an active region and a pad region, wherein the active region has a unit pixel region P of a matrix-type configuration defined by a gate line 12 and a data line 15, and the pad region having a gate pad 22 and a data pad 25 is connected with a driving circuit on an additional PCB (Printed Circuit Board). The pad region is divided into a gate pad region and a data pad region. A gate link line 32 extends from the gate pad 22, the gate pad 22 being formed at an end of the gate link line 32. Also, a data link line 35 extends from the data pad 25, and the data pad 25 is formed at an end of the data link line 35.
More specifically, as shown in FIG. 1-FIG. 2B, the plurality of gate and data lines 12 and 15 crossing each other are formed on the active region of a glass substrate 11, thereby defining the plurality of pixel regions P. A film TFT is formed at a crossing point of the gate and data lines 12 and 15 (to switch a signal). A storage capacitor (not shown) maintains a charging state until addressing a unit pixel region to the next. A pixel electrode 17 is connected with a drain electrode 15b of the TFT to form an electric field controlling a liquid crystal director. A gate insulating layer 13 is formed between the gate line 12 and the data line 15, and a passivation layer 16 is formed between the TFT and the pixel electrode 17.
In the pad region, the plurality of gate link lines 32 and the gate pads 22 extending from the gate lines 12 are formed to apply gate driving signals of a gate driver to the respective gate lines 12. The plurality of data link lines 35 and the data pads 25 extending from the data lines 15 are formed to apply data signals of a data driver to the respective data lines 15, thereby interfacing electrical signals with the external driving circuits.
To drive the LCD device, the gate pad 22 is in contact with the driving circuit supplying the driving signal through an opening through the gate insulating layer 13 and the passivation layer 16 on the gate pad 22. Similarly, the data pad 25 is in contact with the driving circuit supplying the driving signal through an opening through the passivation layer 16 on the data pad 25. A transparent conductive layer 27, being in contact with the gate pad 22 and the data pad 25, is formed in the open portion, thereby preventing oxidation of the gate and data pads 22 and 25.
The plurality of gate pads 22 and data pads 25 are formed in the periphery of the substrate as groups, whereby gate and data driver ICs are mounted to each group in the TCP method. Thus, the various signals are transmitted from the PCB through the driver ICs. The number of the gate and data driver ICs is variable according to a model or a size of the LCD device. In FIG. 1, the gate pad 22 and the data pad 25, to which one gate driver IC 50 and two data driver ICs 51, 52 are mounted, are described in brief.
As described above, the pad electrodes are formed in groups at the portion corresponding to the driver IC. As shown in FIG. 1, if the gate link line 32 is distanced from the portion corresponding to the gate driver IC, the length of the gate link line 32 increases. Meanwhile, if the gate link line 32 is close to the portion corresponding to the gate driver IC, the length of the gate link line 32 decreases. As a result, each of the gate link lines 32 has different lengths with respect to one another. In the same manner, the data link lines 35 have different lengths.
As the link lines have different lengths, the respective link lines have different resistance values. That is, the current passing through the link lines flows at different speeds. For example, in a case of a long link line, the current flows slowly due to the high resistance value of the long link line. In a case of a short link line, the current flow rapidly due to the low resistance value of the short link line. Accordingly, the current speed of a link line at a relatively greater distance from the driver IC is different from the current speed of a link line closer to the driver IC making it impossible to transmit the same signal at the same time.